Global AI MapJOBS / Cerebras
Senior ASIC RTL Design Engineer, AI Hardware
Sunnyvale, CA
Role
The role involves driving chip design, micro-architecture, and RTL development for Cerebras Wafer Scale Engine systems. Candidates must have a Master's degree and 8+ years of experience in high-performance RTL design and integration.
Location: Sunnyvale, CA
Employment: full time
Work pattern: hybrid
Seniority: senior
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Source and currency
This vacancy came from the organization’s official Ashby feed. Source update: 2026-10-07T17:41:20.292+00:00. Check the employer’s page for the complete description, current availability and application terms.