Global AI MapJOBS / Cerebras
Lead RTL Design Engineer
Sunnyvale, CA
Role
The role involves leading RTL design and integration for Cerebras's Wafer Scale Engine, managing external ASIC vendors, and collaborating with verification and physical design teams. Candidates require a Master's degree, 8-15 years of experience in high-performance RTL design, and expertise in networking and high-speed IO.
Location: Sunnyvale, CA
Employment: full time
Work pattern: hybrid
Seniority: lead
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Source and currency
This vacancy came from the organization’s official Ashby feed. Source update: 2026-08-07T21:00:18.824+00:00. Check the employer’s page for the complete description, current availability and application terms.