JOBS / Cerebras

Staff Design Verification Engineer

Sunnyvale, CA

Role

The role involves developing verification strategies, testbenches, and coverage plans for Cerebras's AI chip architecture. Candidates must have 10+ years of Design Verification experience and strong skills in SystemVerilog, UVM, and debugging.

Location: Sunnyvale, CA
Employment: full time
Work pattern: on site
Seniority: senior

SystemVerilogUVMPythonDebuggingCoverage Collection

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Source and currency

This vacancy came from the organization’s official Ashby feed. Source update: 2026-08-12T19:16:56.384+00:00. Check the employer’s page for the complete description, current availability and application terms.

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