Global AI MapJOBS / OpenAI
RTL Design Engineer – Interconnect & Network Datapath
San Francisco
Role
This role involves owning the microarchitecture and RTL implementation of scalable on-chip fabrics and off-chip interfaces for a custom AI accelerator platform. The candidate must have deep expertise in packet networking, interconnects, and SystemVerilog, with experience driving designs from requirements through silicon bring-up.
Location: San Francisco
Employment: unspecified
Work pattern: unspecified
Seniority: senior
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Source and currency
This vacancy came from the organization’s official Ashby feed. Source update: 2026-06-23T23:52:56.682+00:00. Check the employer’s page for the complete description, current availability and application terms.